Semiconductor device

ABSTRACT

To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.14/461,564, filed Aug. 18, 2014, now allowed, which claims the benefitof a foreign priority application filed in Japan as Ser. No. 2013-169830on Aug. 19, 2013, both of which are incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, or a manufacturingmethod. In addition, the present invention relates to a process, amachine, manufacture, or a composition of matter. In particular, thepresent invention relates to, for example, a semiconductor device, adisplay device, a light-emitting device, a power storage device, adriving method thereof, or a manufacturing method thereof. Oneembodiment of the present invention relates to a semiconductor device,particularly to a semiconductor device using an oxide semiconductor.

2. Description of the Related Art

Much attention has been focused on a semiconductor device that retainsdata by using a combination of a transistor in which silicon (Si) isused for a semiconductor layer including a channel formation region (Sitransistor) and a transistor in which an oxide semiconductor (OS) isused for a semiconductor layer including a channel formation region (OStransistor) (see Patent Document 1).

REFERENCE

Patent Document 1: Japanese Published Patent Application No. 2013-009297

SUMMARY OF THE INVENTION

Downsizing of Si transistors is effective in improving the performanceof a semiconductor device. However, downsizing of Si transistors resultsin thinner gate insulating films, thereby posing a problem of leakagecurrent through a gate insulating film.

For this reason, when a node for retaining charge is connected to a gateof a Si transistor as in the above semiconductor device, chargeaccumulated at the node leaks through a gate insulating film of the Sitransistor. Thus, charge retention characteristics of the nodedeteriorate even when the off-state leakage current of the OS transistor(off-state current) is low.

In view of the above, an object of one embodiment of the presentinvention is to provide a novel-structured semiconductor device withexcellent charge retention characteristics of a node for retainingcharge. Another object of one embodiment of the present invention is toprovide a novel-structured semiconductor device in which a transistorused instead of a Si transistor does not degrade the transistorperformance. Another object of one embodiment of the present inventionis to provide a novel-structured semiconductor device that has high areaefficiency by preventing an increase in circuit area due to the increasein the number of components. Another object of one embodiment of thepresent invention is to provide a semiconductor device with a novelstructure.

Note that the descriptions of these objects do not disturb the existenceof other objects. In one embodiment of the present invention, there isno need to achieve all the objects. Objects other than the above objectswill be apparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

One embodiment of the present invention is a semiconductor deviceincluding a first memory circuit that stores data at a first node and asecond node, and a second memory circuit including a third node thatstores the data. The second memory circuit includes a first transistorthat supplies a potential of the data to the third node when the data iswritten; a second transistor including a gate supplied with thepotential held at the third node; a third transistor that charges afirst capacitor connected to one of a source and a drain of the thirdtransistor when the data is not read; and a fourth transistor thatdistributes charge stored in the first capacitor to a second capacitor,when the data is read. When the data is read, the second transistormakes a potential held in the second capacitor a potential obtained byinverting logic of the data, in accordance with the potential of thethird node. Each of the first transistor and the second transistorcontains an oxide semiconductor in a semiconductor layer including achannel formation region.

In the semiconductor device of one embodiment of the present invention,each of the third transistor and the fourth transistor preferablycontains silicon in a semiconductor layer including a channel formationregion.

In the semiconductor device of one embodiment of the present invention,the first transistor and the second transistor are preferably stackedover the third transistor and the fourth transistor.

In the semiconductor device of one embodiment of the present invention,the second transistor is preferably connected to a fifth transistorcontaining silicon in a semiconductor layer including a channelformation region, to form a Darlington pair.

In the semiconductor device of one embodiment of the present invention,each of the first transistor and the second transistor preferablyincludes a backgate electrode.

In the semiconductor device of one embodiment of the present invention,a transistor that supplies a potential for initializing the potentialheld in the second capacitor is preferably electrically connected to oneof electrodes of the second capacitor.

In the semiconductor device of one embodiment of the present invention,the capacitance of the first capacitor is preferably larger than that ofthe second capacitor.

In the semiconductor device of one embodiment of the present invention,the thickness of a gate insulating film of the second transistor islarger than that of a gate insulating film of the third transistor andthe fourth transistor.

The semiconductor device of one embodiment of the present inventionpreferably includes an inverter circuit that inverts the potential heldin the second capacitor and supplies the inverted potential to thesecond node.

One embodiment of the present invention can provide a novel-structuredsemiconductor device with excellent charge retention characteristics ofa node for retaining charge. One embodiment of the present invention canprovide a novel-structured semiconductor device in which a transistorused instead of a Si transistor does not degrade the transistorperformance. Furthermore, one embodiment of the present invention canprovide a novel-structured semiconductor device that has high areaefficiency by preventing an increase in circuit area due to the increasein the number of components.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings,

FIG. 1 is a circuit diagram of one embodiment of the present invention;

FIG. 2 is a circuit diagram of one embodiment of the present invention;

FIG. 3 is a timing chart of one embodiment of the present invention;

FIG. 4 is a timing chart of one embodiment of the present invention;

FIG. 5 is a circuit diagram of one embodiment of the present invention;

FIG. 6 is a circuit diagram of one embodiment of the present invention;

FIG. 7 is a circuit diagram of one embodiment of the present invention;

FIG. 8 is a circuit diagram of one embodiment of the present invention;

FIG. 9 is a circuit diagram of one embodiment of the present invention;

FIG. 10 is a circuit diagram of one embodiment of the present invention;

FIG. 11 is a circuit diagram of one embodiment of the present invention;

FIG. 12 is a circuit diagram of one embodiment of the present invention;

FIG. 13 is a cross-sectional view of one embodiment of the presentinvention;

FIG. 14A is a flowchart showing fabrication steps of a semiconductordevice, and FIG. 14B is a perspective schematic view of thesemiconductor device;

FIGS. 15A to 15E each illustrate an electronic device including asemiconductor device;

FIG. 16 is a circuit diagram of one embodiment of the present invention;

FIG. 17 is a circuit diagram of one embodiment of the present invention;

FIG. 18 is a circuit diagram of one embodiment of the present invention;

FIG. 19 is a circuit diagram of one embodiment of the present invention;

FIG. 20 is a circuit diagram of one embodiment of the present invention;

FIG. 21 is a circuit diagram of one embodiment of the present invention;

FIG. 22 is a circuit diagram of one embodiment of the present invention;

FIG. 23 is a circuit diagram of one embodiment of the present invention;and

FIG. 24 is a circuit diagram of one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments will be described below with reference to the drawings. Notethat the embodiments can be implemented with various modes, and it willbe readily appreciated by those skilled in the art that modes anddetails can be changed in various ways without departing from the spiritand scope of the present invention. Thus, the present invention shouldnot be interpreted as being limited to the following description of theembodiments. Note that in structures of the present invention describedbelow, reference numerals denoting the same portions are used in commonin different drawings.

In the drawings, the size, the layer thickness, or the region isexaggerated for clarity in some cases. Therefore, embodiments of thepresent invention are not limited to such a scale. Note that thedrawings are schematic views showing ideal examples, and embodiments ofthe present invention are not limited to shapes or values shown in thedrawings. For example, variation in signal, voltage, or current due tonoise or difference in timing can be included.

In this specification and the like, a transistor is an element having atleast three terminals: a gate, a drain, and a source. The transistor hasa channel region between the drain (a drain terminal, a drain region, ora drain electrode) and the source (a source terminal, a source region,or a source electrode), and current can flow through the drain, thechannel region, and the source.

Here, since the source and the drain of the transistor may changedepending on the structure, operating conditions, and the like of thetransistor, it is difficult to define which is a source or a drain.Thus, it is possible that a portion functioning as the source and aportion functioning as the drain are not called a source and a drain,and that one of the source and the drain is referred to as a firstelectrode and the other is referred to as a second electrode.

In this specification and the like, ordinal numbers such as first,second, and third are used to avoid confusion among components, and thusdo not limit the number of the components.

In this specification and the like, the expression “A and B areconnected” means the case where A and B are electrically connected toeach other in addition to the case where A and B are directly connectedto each other. Here, the expression “A and B are electrically connected”means the case where electric signals can be transmitted and receivedbetween A and B when an object having any electric action exists betweenA and B.

In this specification and the like, terms for explaining arrangement,such as over and under, are used for convenience to describe thepositional relation between components with reference to drawings.Furthermore, the positional relation between components is changed asappropriate in accordance with a direction in which each component isdescribed. Thus, there is no limitation on terms used in thisspecification, and description can be made as appropriate depending onthe situation.

In this specification and the like, the layout of circuit blocks in adrawing specifies the positional relation for description. Thus, evenwhen a drawing shows that different functions are achieved in differentcircuit blocks, an actual circuit block may be configured so that thedifferent functions are achieved in the same circuit or region. Inaddition, the function of each circuit block in a drawing is specifiedfor description. Thus, even when one circuit block is illustrated, anactual circuit or region may be configured so that processing which isshown as being performed in the one circuit block is performed in aplurality of circuit blocks.

In this specification and the like, voltage often refers to a differencebetween a given potential and a reference potential (e.g., a groundpotential). Accordingly, voltage, potential, and potential differencecan also be referred to as potential, voltage, and voltage difference,respectively. Note that voltage refers to a difference betweenpotentials of two points, and potential refers to electrostatic energy(electric potential energy) of a unit charge at a given point in anelectrostatic field.

In this specification and the like, the term “parallel” indicates thatthe angle formed between two straight lines ranges from −10° to 10°, andaccordingly also includes the case where the angle ranges from −5° to5°. The term “perpendicular” indicates that the angle formed between twostraight lines ranges from 80° to 100°, and accordingly also includesthe case where the angle ranges from 85° to 95°.

In this specification and the like, the trigonal and rhombohedralcrystal systems are included in the hexagonal crystal system.

Embodiment 1

In this embodiment, a circuit structure and operation of a semiconductordevice will be described.

Note that a semiconductor device refers to a device including asemiconductor element. The semiconductor device includes a drivercircuit for driving a circuit including a semiconductor element, forexample. Note that the semiconductor device may include a drivercircuit, a power supply circuit, or the like provided over anothersubstrate.

FIG. 1 is a circuit diagram illustrating an example of a semiconductordevice 10 capable of storing 1-bit data. Note that in reality, aplurality of semiconductor devices connected are provided.

The semiconductor device 10 illustrated in FIG. 1 includes a memorycircuit 110 and a memory circuit 120.

The memory circuit 110 includes a node Node_in and a node Node_out thatare capable of holding a potential corresponding to data “1” or data “0”as data while the power supply voltage is applied. The memory circuit110 is supplied with the power supply voltage based on a high powersupply potential VDD supplied to a power supply line VL and a groundpotential supplied to a ground line as a low power supply potential.Note that the memory circuit 110 may be referred to as a first memorycircuit.

Note that in general, a potential and a voltage are relative values;therefore, a ground potential is not always 0 V.

Data held at the node Node_in and the node Node_out is 1-bit data. Forexample, an L-level potential is stored as data “0” and an H-levelpotential is stored as data “1”.

Potentials held at the node Node_in and the node Node_out are tomaintain data with the same potential. The node Node_in and the nodeNode_out may be the same node. When the node Node_in and the nodeNode_out are different nodes, one of them is supplied with inverteddata.

While the power supply voltage is applied, data held at the node Node_inand the node Node_out is changed by data D and a clock signal C that areinput to the memory circuit 110. The potentials held at the node Node_inand the node Node_out are output as an output signal Q while the powersupply voltage is applied.

An inverted clock signal CB, a reset signal, and/or the like in additionto the data D and the clock signal C may be input to the memory circuit110. Moreover, an input clock signal may be a plurality of clock signalshaving different phases.

The memory circuit 110 is a volatile register, a flip-flop, or a latchcircuit. For example, when the memory circuit 110 is a register, a Dregister, a T register, a JK register, a SR register, or the like can beused.

While application of the power supply voltage is stopped, a potentialheld at the node Node_in is stored in the memory circuit 120. Thepotential stored in the memory circuit 120 is restored at the nodeNode_out in the memory circuit 110 when application of the power supplyvoltage is restarted. Note that the potentials held at the node Node_inand the node Node_out in the memory circuit 110 are lost whenapplication of the power supply voltage to the memory circuit 110 isstopped.

Stopping application of the power supply voltage in the semiconductordevice 10 is switching the potential of the power supply line VL fromthe high power supply potential VDD to the ground potential. Note that aswitch may be provided between the power supply line VL and the memorycircuit 110, in which case application of the power supply voltage canbe stopped by turning off the switch.

Restarting application of the power supply voltage in the semiconductordevice 10 is switching the potential of the power supply line VL fromthe ground potential to the high power supply potential VDD. A switchmay be provided between the power supply line VL and the memory circuit110, in which case application of the power supply voltage can berestarted by turning on the switch.

The memory circuit 120 includes a node Node_M capable of holding apotential corresponding to data “1” or data “0” as data even whileapplication of the power supply voltage is stopped. Like the memorycircuit 110, the memory circuit 120 is supplied with the power supplyvoltage based on the high power supply potential VDD supplied to thepower supply line VL and the ground potential supplied to a ground lineas the low power supply potential. Note that the memory circuit 120 maybe referred to as a second memory circuit.

The memory circuit 120 in FIG. 1 includes a transistor 121 (alsoreferred to as first transistor), a capacitor 122, a transistor 123(also referred to as second transistor), a transistor 124 (also referredto as third transistor), a transistor 125 (also referred to as fourthtransistor), a capacitor 126 (also referred to as first capacitor), acapacitor 127 (also referred to as second capacitor), and an invertercircuit 128.

In FIG. 1, for explanation, a node connected to one electrode of thecapacitor 126 is shown as a node V_C1 and a node connected to oneelectrode of the capacitor 127 is shown as a node V_C2.

A gate of the transistor 121 is supplied with a control signal WE (alsoreferred to as write control signal). One of a source and a drain of thetransistor 121 is supplied with data held at the node Node_in. The datais transferred through the transistor 121 and is held at the node Node_Mconnected to the other of the source and the drain of the transistor121. As an example, the transistor 121 is an n-channel transistor in thefollowing description.

The potential of the node Node_M is held at one electrode of thecapacitor 122. The other electrode of the capacitor 122 is supplied witha fixed potential, here, the ground potential of a ground line. Notethat the capacitor 122 can be eliminated when the transistor 123 haslarge gate capacitance, for example.

A gate of the transistor 123 is supplied with a potential of the nodeNode_M. One of a source and a drain of the transistor 123 is suppliedwith a potential of the node V_C2, and the other thereof is suppliedwith the ground potential. As an example, the transistor 123 is ann-channel transistor in the following description.

A gate of the transistor 124 is supplied with a control signal RE_b(also referred to as inverted read control signal). One of a source anda drain of the transistor 124 is supplied with a potential of the powersupply line VL. The potential of the power supply line VL is transferredthrough the transistor 124 and is held at the node V_Cl connected to theother of the source and the drain of the transistor 124. As an example,the transistor 124 is an n-channel transistor in the followingdescription.

The potential of the node V_C1 is held at one electrode of the capacitor126. The other electrode of the capacitor 126 is supplied with a fixedpotential, here, the ground potential of a ground line.

A gate of the transistor 125 is supplied with a control signal RE (alsoreferred to as read control signal). One of a source and a drain of thetransistor 125 is supplied with a potential of the node V_C1. Thepotential of the node V_C1 is transferred through the transistor 125 andis held at the node V_C2 connected to the other of the source and thedrain of the transistor 125. As an example, the transistor 125 is ann-channel transistor in the following description.

The potential of the node V_C2 is held at one electrode of the capacitor127. The other electrode of the capacitor 127 is supplied with a fixedpotential, here, the ground potential of a ground line.

An input terminal of the inverter circuit 128 is supplied with apotential of the node V_C2. The inverter circuit 128 supplies apotential of its output terminal to the node Node_out in the memorycircuit 110. The potential of the output terminal of the invertercircuit 128 corresponds to a potential corresponding to data stored inthe memory circuit 120, that is, a potential of the node Node_M.

The control signal WE is a signal for switching between continuity anddiscontinuity between the node Node_in and the node Node_M. With thecontrol signal WE, the transistor 121 can function as a switch capableof being turned on and off When the transistor 121 is an n-channeltransistor, the transistor 121 is turned on when the control signal WEis at H level and is turned off when the control signal WE is at Llevel.

With the structure illustrated in FIG. 1, a potential corresponding todata is held at the node Node_M, and the semiconductor device 10 storesthe data. By turning off the transistor 121, the node Node_M holds thepotential for a long time so that data is stored.

To prevent a potential change associated with charge transfer at thenode Node_M and retain data for a long time, the following two featuresare required: one is extremely low leakage current between the sourceand the drain of the transistor 121, and the other is extremely lowleakage current through a gate insulating film of the transistor 123.

In view of the above, a transistor with extremely low leakage currentbetween its source and drain is used as the transistor 121. Here, lowleakage current means that a normalized leakage current per micrometerin channel width at room temperature is 10 zA/μm or lower. Since leakagecurrent is preferably as low as possible, the normalized leakage currentis preferably 1 zA/μm or lower, more preferably 10 yA/μm or lower, stillmore preferably 1 yA/μm or lower. Note that a voltage between the sourceand the drain in this case is approximately 0.1 V, 5 V, or 10 V, forexample. An example of a transistor with extremely low leakage currentbetween its source and drain is a transistor in which a channel isformed in an oxide semiconductor.

As the transistor 123, a transistor with extremely low leakage currentthrough a gate insulating film is used. The leakage current through agate insulating film of the transistor 123 is preferably as low as theleakage current between the source and the drain of the transistor 121.In a Si transistor included in the semiconductor device 10, a gateinsulating film is reduced in thickness with reduction in the transistorsize; thus, a leakage current through the gate insulating film becomeshigher. On the other hand, the size of an OS transistor is notnecessarily made smaller than that of a Si transistor; therefore, a gateinsulating film of the OS transistor can be made thick to reduce leakagecurrent through the gate insulating film.

The leakage current of the transistor 123 through the gate insulatingfilm is preferably 10 yA or lower, more preferably 1 yA or lower. Whenthe leakage current is 10 yA or lower and the capacitance of the nodeNode_M and the allowable voltage fluctuation are assumed to be 10 fF and0.3 V, respectively, the node Node_M can hold charge for about 10 years(t≈3×10⁸ s).

When the transistors 121 and 123 are each a transistor with a channelwidth and length of 1 μm and 1 μm, to achieve a leakage current of 10 yAor lower to enable the above charge retention, the equivalent oxidethickness of the gate insulating film is approximately 6 nm or more. Toachieve the above low leakage current, the thickness of the gateinsulating film of the OS transistor is made different from that of agate insulating film of a Si transistor provided in another layer.Specifically, the gate insulating film of the transistors 121 and 123 ismade thicker than that of the transistors 124 and 125 that are Sitransistors. This is preferable because a reduction in the thickness ofthe gate insulating film of the Si transistor does not adversely affectcharge retention at the node Node_M.

The control signal RE_b is a signal for switching between continuity anddiscontinuity between the power supply line VL and the node V_C1 . Withthe control signal RE_b, the transistor 124 can function as a switchcapable of being turned on and off When the transistor 124 is ann-channel transistor, the transistor 124 is turned on when the controlsignal RE_b is at H level and is turned off when the control signal RE_bis at L level. The control signal RE_b turns on the transistor 124 whilea potential held at the node Node_M is not supplied to the nodeNode_out, that is, while data is not read from the memory circuit 120.

The control signal RE is a signal for switching between continuity anddiscontinuity between the node V_C1 and the node V_C2. With the controlsignal RE, the transistor 125 can function as a switch capable of beingturned on and off. When the transistor 125 is an n-channel transistor,the transistor 125 is turned on when the control signal RE is at H leveland is turned off when the control signal RE is at L level. The controlsignal RE turns on the transistor 125 while a potential held at the nodeNode_M is supplied to the node Node_out, that is, while data is readfrom the memory circuit 120.

Note that the control signal RE_b and the control signal RE are oppositein phase. In other words, these signals alternately turn on and off thecorresponding transistors 124 and 125, thereby making only one oftransistors 124 and 125 on.

H-level potentials of the control signal WE, the control signal RE, andthe control signal RE_b are preferably higher than the high power supplypotential VDD. Specifically, such an H-level potential is preferablyhigher than the high power supply potential VDD by the threshold voltageof a transistor whose gate is supplied with the signal, in which casepotentials held at the nodes can be prevented from varying depending onthe threshold voltages of the transistors.

The potential of the node Node_M is a potential corresponding data atthe node Node_in. Specifically, the node Node_M holds an H-levelpotential when data at the node Node_in is data “1”, whereas the nodeNode_M holds an L-level potential when data at the node Node_in is data“0”. Thus, the transistor 123 is turned on when data “1” is stored inthe memory circuit 120 and is turned off when data “0” is stored in thememory circuit 120.

The potentials of the node V_C1 and the node V_C2 are switched inresponse to the control signal RE and the control signal RE_b. When thetransistor 124 is turned on and the transistor 125 is turned off, thecapacitor 126 is charged by the power supply line VL, and the potentialof the power supply line VL, that is, an H-level potential correspondingto the high power supply potential VDD is held at the node V_C1Meanwhile, when the transistor 124 is turned off and the transistor 125is turned on, charge stored in the capacitor 126 in advance isdistributed to the capacitor 127. In this charge distribution, changesin the potentials of the node V_C1 and the node V_C2 vary depending onthe potential of the node Node_M.

Specifically, when the potential of the node Node_M is an H-levelpotential, the transistor 123 is turned on, and the potential of thenode V_C1 becomes the ground potential. When the transistor 125 isturned on while the transistor 123 is on, charge held at the node V_C1and the node V_C2 is released.

When the potential of the node Node_M is an L-level potential, thetransistor 123 is turned off, and the potential of the node V_C1 becomesa potential obtained by charge distribution among the capacitors 126 and127. When the transistor 125 is turned on while the transistor 123 isoff, the node V_C1 and the node V_C2 are brought into an electricallyfloating state. The potentials of the node V_C1 and the node V_C2 becomeequal to each other because charge stored at the nodes is distributed tothe capacitors 126 and 127.

To make the potential of the node V_C2 closer to an H-level potential bycharge distribution among the node V_C1 and the node V_C2, thecapacitance of the capacitor 126 is set larger than that of thecapacitor 127. This decreases the amount of reduction in the potentialof the node V_C2 from the H-level potential, which is the potential ofthe node V_C1, when continuity is established between the node V_C1 andthe node V_C2.

When the node Node_M has an L-level potential, the potential of the nodeV_C2 is controlled to be close to an H-level potential, so that thepotential of a signal output through the inverter circuit 128 becomes apotential obtained by reversing the potential of the node V_C2, namelythe L-level potential, which is the potential of the node Node_M.Meanwhile, when the node Node_M has an H-level potential, the potentialof the node V_C2 becomes the ground potential, that is, the L-levelpotential, and the potential of a signal output through the invertercircuit 128 becomes a potential obtained by reversing the potential ofthe node V_C2, namely the H-level potential, which is the potential ofthe node Node_M. Accordingly, the inverter circuit 128 can output datato the node Node_out in response to a change in the potential of thenode V_C2, specifically outputs data “1” when the node V_C2 has anH-level potential and outputs data “0” when the node V_C2 has an L-levelpotential. The output data corresponds to the aforementioned data at thenode Node_in.

In the structure of FIG. 1, whether data stored in the memory circuit120 is restored to the memory circuit 110 is determined depending onwhether charge stored in the capacitor 126 in advance is distributed tothe capacitor 127. This restoration operation can be performed only byswitching the control signal RE and the control signal RE_b.

As described above, in the structure of this embodiment illustrated inFIG. 1, an OS transistor including a gate insulating film that isthicker than that in a Si transistor is provided as the transistor 123whose gate is connected to the node Node_M for retaining charge. Inaddition, charge is stored in the capacitor 126, and data at the nodefor retaining charge is read based on whether the stored charge isdistributed to the capacitor 127. In the above structure, since a Sitransistor, in which leakage current through a gate insulating filmoccurs, is not used as a transistor connected to the node for retainingcharge, charge retention characteristics of the node can be improved.

In the structure of this embodiment illustrated in FIG. 1, charging ofthe capacitor 126, which is necessary for data reading, can beautomatically performed by supply of the high power supply potential tothe power supply line VL. For this reason, a signal for controllingcharging of the capacitor 126 is not required. Consequently, thesequence of restoring data in the memory circuit 120 to the memorycircuit 110 can be controlled only by the control signal RE and thecontrol signal RE_b; thus, data can be restored at high speed. Moreover,the restoration sequence can be performed any time until the next datais supplied to the node Node_M.

In the structure of the semiconductor device 10 in FIG. 1, the capacitor127 and the inverter circuit 128 can be omitted. FIG. 16 is a diagram ofthe semiconductor device 10 without the capacitor 127 and the invertercircuit 128.

In the structure of the semiconductor device 10 in FIG. 1, the capacitor127 can be omitted. FIG. 17 is a diagram of the semiconductor device 10without the capacitor 127. By using parasitic capacitance of a wiring orgate capacitance of a transistor, the semiconductor device in FIG. 17can operate in a manner similar to that of FIG. 1.

In the structure of the semiconductor device 10 in FIG. 1, the capacitor122 can be omitted. FIG. 18 is a diagram of the semiconductor device 10without the capacitor 122. By using parasitic capacitance of a wiring orgate capacitance of a transistor, the semiconductor device in FIG. 18can operate in a manner similar to that of FIG. 1.

In the structure of the semiconductor device 10 in FIG. 1, the otherelectrode of each of the capacitors 122, 126, and 127 can be connectedto a variety of wirings. For example, a fixed potential supplied to atleast one of these electrodes may be a low power supply potential VSS.FIG. 19 illustrates an example of a diagram in which a wiring forapplying the low power supply potential is connected to the capacitorsand the other of the source and the drain of the transistor 123. Asanother example, it is possible that a fixed potential supplied to theother electrode of the capacitor 122 is the low power supply potentialVSS and a fixed potential supplied to the other electrode of each of thecapacitors 126 and 127 is the ground potential. FIG. 22 illustrates anexample of a diagram showing this structure. As another example, it ispossible that a fixed potential supplied to the other electrode of thecapacitor 122 is the potential of the power supply line VL and a fixedpotential supplied to the other electrode of each of the capacitors 126and 127 is the ground potential. FIG. 23 illustrates an example of adiagram showing this structure. As another example, it is possible thata fixed potential supplied to the other electrode of each of thecapacitors 126 and 127 is the potential of the power supply line VL anda fixed potential supplied to the other electrode of the capacitor 122is the ground potential. FIG. 24 illustrates an example of a diagramshowing this structure.

In the structure of the semiconductor device 10 in FIG. 1, the invertercircuit 128 can be replaced with an amplifier circuit or the like. Forexample, the inverter circuit 128 can be replaced with a buffer 128_BUFas illustrated in FIG. 20.

Moreover, in the structure of the semiconductor device 10 in FIG. 1, theinverter circuit 128 can be replaced with a circuit using an operationalamplifier, a voltage follower circuit, or the like. For example, theinverter circuit 128 can be replaced with an amplifier 128_AMP asillustrated in FIG. 21.

Next, an example of the operation of the semiconductor device 10 will bedescribed with reference to FIGS. 2 to 4.

FIG. 2 is a circuit diagram of the semiconductor device 10 in which theconfiguration of the memory circuit 110 in FIG. 1 is specifically shownto explain an example of specific operation.

The memory circuit 110 includes the node Node_in and the node Node_outthat are capable of holding a potential corresponding to data “1” ordata “0” as data while the power supply voltage is applied. Note that inthe example of the circuit diagram in FIG. 2, the node Node_in and thenode Node_out are the same node.

As an example, FIG. 2 illustrates that the memory circuit 110 includes aswitch 111, an inverter circuit 112, an inverter circuit 113, a switch114, and an inverter circuit 115.

As an example, FIG. 2 illustrates that the data D, the clock signal C,and the inverted clock signal CB are input to the memory circuit 110 andthe memory circuit 110 outputs the output signal Q. The memory circuit110 is supplied with the power supply voltage based on potentialssupplied to the power supply line VL and a ground line.

One terminal of the switch 111 is supplied with the data D. The on/offstate of the switch 111 is controlled by the clock signal C so that thedata D is captured in the memory circuit 110. The captured data is heldby an inverter loop consisting of the inverter circuits 112 and 113. Theon/off state of the switch 114 is controlled by the inverted clocksignal CB so that data is held. Then, a signal obtained by inverting thedata D held at the node Node_in is inverted again by the invertercircuit 115, whereby the output signal Q corresponding to the data D canbe output.

In the structure of FIG. 2, data is stored in the memory circuit 120 andrestored to the memory circuit 110 through a selector 130. Depending onthe control signal RE, the selector 130 controls whether to return asignal at the node Node_in to the inverter loop or return a signaloutput from the memory circuit 120 to the node Node_in. In a periodduring which data is held in the memory circuit 110, the selector 130 issupplied with an L-level control signal RE and is thus switched so thata signal at the node Node_in is returned to the inverter loop. In aperiod during which data stored in the memory circuit 120 is restored tothe memory circuit 110, the selector 130 is supplied with an H-levelcontrol signal RE and is thus switched so that a signal output from thememory circuit 120 is returned to the node Node_in.

An inverter circuit 131 is a circuit that generates a control signalcorresponding to the control signal RE_b shown in FIG. 1. An inputterminal of the inverter circuit 131 is supplied with the control signalRE. A signal output from an output terminal of the inverter circuit 131is supplied to the gate of the transistor 124.

FIG. 3 is a timing chart of the semiconductor device 10 illustrated inFIG. 2. FIG. 3 shows the case where an H-level potential is stored atthe node Node_M in the memory circuit 120 and then restored.

The timing chart in FIG. 3 shows changes in signals or potentials of theclock signal C, the inverted clock signal CB, the data D, the nodeNode_in, the output signal Q, the control signal WE, the control signalRE, the power supply line VL, the node Node_M, the node V_C1, and thenode V_C2.

In the timing chart in FIG. 3, periods P1 to P4 show the state of thesemiconductor device 10. The period P1 is a normal operation period. Theperiod P2 is a transition period for operation stop. The period P3 is anoperation stop period. The period P4 is a transition period foroperation restart. Moreover, in the timing chart in FIG. 3, times T1 toT14 are used to explain the operation.

In the period P1 for normal operation, H-level signals and L-levelsignals are alternately supplied as the clock signal C and the invertedclock signal CB so that the clock signal C and the inverted clock signalCB are opposite in phase. The control signal RE and the control signalWE are at L level. The high power supply potential is supplied to thepower supply line VL. At this time, the memory circuit 110 can operateas a normal register or flip-flop. Furthermore, in the period P1, thenode V_C1 is charged with the high power supply potential of the powersupply line VL to have an H-level potential, and the node V_C2 isfloating.

In the period P2, which is a transition period for operation stop, fixedpotentials are supplied as the clock signal C and the inverted clocksignal CB. In other words, the clock signal C is fixed at L level andthe inverted clock signal CB is fixed at H level. In a period betweenthe time T6 and the time T7, the control signal WE is set at H level anddata “1” held at the node Node_in in the memory circuit 110, here anH-level potential, is stored at the node Node_M.

In the period P3 for operation stop, the power supply line VL is set atthe ground potential, that is, an L-level potential. That is,application of the power supply voltage to the semiconductor device 10is stopped. At this time, the control signal RE and the control signalWE are at L level. The data D, the clock signal C, and the invertedclock signal CB are at L level. Note that it is possible that the powersupply line VL is fixed at the high power supply potential VDD and thepotential of the ground line is switched from the ground potential tothe high power supply potential VDD to stop application of the powersupply voltage.

In the period P3, which is an operation stop period, power consumptionof the semiconductor device 10 can be extremely small becauseapplication of the power supply voltage is stopped. Note that thepotential of the node Node_M is kept constant because leakage current ofthe transistor 121 and the transistor 123 hardly flows.

In the period P4, which is the transition period for operation restart,the potentials of the wirings are sequentially brought back to thestates at the end of the preceding normal operation period, that is, atthe time T5. First, at the time T9, the power supply line VL is set at Hlevel to have the high power supply potential. Thus, the node V_C1 ischarged. Note that the node Node_in is floating until data is fixed. Atthe time when the node V_C1 reaches H level by charging (at the time T11in FIG. 3), the control signal RE is set at H level. Thus, thepotentials of the node V_C1 and the node V_C2 change in accordance withthe potential of the node Node_M. According to FIG. 3, the transistor123 is turned on, so that the potentials of the node V_C1 and the nodeV_C2 become L level. When the potential of the node V_C2 becomes Llevel, an output signal of the inverter circuit 128 becomes H level.When the control signal RE is set at H level, the selector 130 suppliesan output signal of the inverter circuit 128 to the node Node_in;consequently, the potential of the node Node_in in the memory circuit110 is returned to the H-level potential, which is data at the time T5.

Then, when supply of the clock signal C and the inverted clock signal CBis started again from the time T13, normal operation following theoperation at the time T5 can be resumed.

Next, FIG. 4 shows the case where an L-level potential is stored at thenode Node_M in the memory circuit 120 and then restored.

As in FIG. 3, the timing chart in FIG. 4 shows changes in signals orpotentials of the clock signal C, the inverted clock signal CB, the dataD, the node Node_in, the output signal Q, the control signal WE, thecontrol signal RE, the power supply line VL, the node Node_M, the nodeV_C1, and the node V_C2.

As in FIG. 3, the periods P1 to P4 in the timing chart of FIG. 4 showthe state of the semiconductor device 10. The period P1 is a normaloperation period. The period P2 is a transition period for operationstop. The period P3 is an operation stop period. The period P4 is atransition period for operation restart. Moreover, in the timing chartin FIG. 4, times tl to t14 are used to explain the operation.

In the period P1 for normal operation, H-level signals and L-levelsignals are alternately supplied as the clock signal C and the invertedclock signal CB so that the clock signal C and the inverted clock signalCB are opposite in phase. The control signal RE and the control signalWE are at L level. The high power supply potential is supplied to thepower supply line VL. At this time, the memory circuit 110 can operateas a normal register or flip-flop. Furthermore, in the period P1, thenode V_C1 is charged with the high power supply potential of the powersupply line VL to have an H-level potential, and the node V_C2 isfloating.

In the period P2, which is a transition period for operation stop, fixedpotentials are supplied as the clock signal C and the inverted clocksignal CB. In other words, the clock signal C is fixed at L level andthe inverted clock signal CB is fixed at H level. In a period betweenthe time t6 and the time t7, the control signal WE is set at H level anddata “0” held at the node Node_in in the memory circuit 110, here anL-level potential, is stored at the node Node_M.

In the period P3 for operation stop, the power supply line VL is set atthe ground potential, that is, an L-level potential. That is,application of the power supply voltage to the semiconductor device 10is stopped. At this time, the control signal RE and the control signalWE are at L level. The data D, the clock signal C, and the invertedclock signal CB are at L level.

In the period P3, which is an operation stop period, power consumptionof the semiconductor device 10 can be extremely small becauseapplication of the power supply voltage is stopped. Note that thepotential of the node Node_M is kept constant because leakage current ofthe transistor 121 and the transistor 123 hardly flows.

In the period P4, which is the transition period for operation restart,the potentials of the wirings are sequentially brought back to thestates at the end of the preceding normal operation period, that is, atthe time t5. First, at the time t9, the power supply line VL is set at Hlevel to have the high power supply potential. Thus, the node V_C1 ischarged. Note that the node Node_in is floating until data is fixed. Atthe time when the node V_C1 reaches H level by charging (at the time tllin FIG. 4), the control signal RE is set at H level. Thus, thepotentials of the node V_C1 and the node V_C2 change in accordance withthe potential of the node Node_M. According to FIG. 4, the transistor123 is turned off, so that charge stored at the node V_C1 is distributedto the node V_C2 through the transistor 125; thus, the potential of thenode V_C1 decreases and the potential of the node V_C2 increases.Setting the capacitance of the capacitor 126 larger than that of thecapacitor 127 increases the potential of the node V_C2 to a value closeto the H-level potential. The increase in the potential of the node V_C2results in an L-level output signal of the inverter circuit 128. Whenthe control signal RE is set at H level, the selector 130 supplies anoutput signal of the inverter circuit 128 to the node Node_in;consequently, the potential of the node Node_in in the memory circuit110 is returned to the L-level potential, which is data at the time t5.

Then, when supply of the clock signal C and the inverted clock signal CBis started again from the time t13, normal operation following theoperation at the time t5 can be resumed.

In the operation of the semiconductor device described so far in thisembodiment, application of the power supply voltage can be stopped asappropriate with data storage and restoration in the memory circuits 110and 120. Thus, power consumption can be reduced.

In the semiconductor device described in this embodiment, data storagein the memory circuits 110 and 120 can be controlled by the conductionstate of the transistor 121; thus, operation delay is less than that ina structure where data is stored in an external memory circuit such asflash memory. Furthermore, the semiconductor device can be configured sothat data is stored in the memory circuit 120 before application of thepower supply voltage is stopped and data is held in the memory circuit110 in the other periods, during which the power supply voltage isapplied. Consequently, the operation of storing data can be performed athigh speed while the power supply voltage is applied, and operationdelay can be suppressed. In the semiconductor device of this embodiment,the OS transistors and the Si transistors can be stacked; thus, theincrease in the circuit area due to the increase in the number ofelements can be prevented. The semiconductor device therefore has higharea efficiency.

As described above, data can be saved from the memory circuit 110 to thememory circuit 120 and restored from the memory circuit 120 to thememory circuit 110 as in the timing charts of FIGS. 3 and 4.

Note that the inverter circuit 128 shown in FIGS. 1 and 2 is preferablya CMOS inverter. FIG. 5 shows a specific circuit diagram.

The inverter circuit 128 illustrated in FIG. 5 includes a p-channeltransistor 128_p supplied with the high power supply potential from thepower supply line VL and an n-channel transistor 128_n supplied with theground potential.

When the inverter circuit 128 is a CMOS circuit and the node V_C2 isconnected to gates of the transistors 128_p and 128_n as illustrated inFIG. 5, by turning on one of these transistors depending on the amountof charge stored at the node V_C2, a signal having a potential obtainedby reversing the potential of the node V_C2 can be output withoutreducing the amount of stored charge.

One embodiment of the present invention described above is asemiconductor device with improved charge retention characteristics of anode for retaining charge.

This embodiment can be combined with any of the other embodiments asappropriate.

Embodiment 2

In this embodiment, variation examples of the semiconductor device 10 inEmbodiment 1 will be described. Here, Variations examples 1 to 7 will bedescribed with reference to FIGS. 6 to 12.

VARIATION EXAMPLE 1

FIG. 6 is a circuit diagram illustrating a configuration example of asemiconductor device 30 different from the semiconductor device 10 ofFIG. 1 in that a bipolar transistor 141 (also referred to as fifthtransistor) is connected to the source and the drain of the transistor123.

The amount of current flowing through the transistor 123, which is theOS transistor, is smaller than that flowing through a Si transistor. Forthis reason, by connecting a collector of the bipolar transistor 141 toone of the source and the drain of the transistor 123 and connecting abase of the bipolar transistor 141 to the gate of the transistor 123 tohave a Darlington configuration, the amount of current for controllingthe potential of the node V_C2 can be increased while taking advantageof low gate leakage current of the OS transistor. The flow of currentthrough the bipolar transistor 141 in the Darlington configuration iscontrolled by the on/off state of the transistor 123.

The configuration illustrated in FIG. 6 can increase the amount ofcurrent flowing depending on the conduction state of the transistor 123,which is switched by the potential of the node Node_M. Thus, even if thetransistor performance is degraded when the transistor 123 is not a Sitransistor, the potential of the node V_C2 can be controlled at higherspeed by using a combination of the transistor 123 and a transistorachieving higher performance than a Si transistor.

VARIATION EXAMPLE 2

FIG. 7 is a circuit diagram illustrating a configuration example of asemiconductor device 40 different from the semiconductor device 10 ofFIG. 1 in that a transistor 142 that is a Si transistor is connected tothe source and the drain of the transistor 123.

The amount of current flowing through the transistor 123, which is theOS transistor, is smaller than that flowing through the Si transistor.For this reason, one of a source and a drain of the Si transistor 142 isconnected to one of the source and the drain of the transistor 123 and agate of the Si transistor 142 is connected to the other of the sourceand the drain of the transistor 123 to form a Darlington pair as in FIG.6.

The configuration in FIG. 7 provides an effect similar to that obtainedwith the configuration in FIG. 6. In other words, the amount of currentflowing depending on the conduction state of the transistor 123, whichis switched by the potential of the node Node_M, can be increased. Thus,the potential of the node V_C2 can be controlled at higher speed.

VARIATION EXAMPLE 3

FIG. 8 is a circuit diagram illustrating a configuration example of asemiconductor device 50 different from the semiconductor device 10 ofFIG. 1 in that a transistor 143 for initializing the potential of thenode V_C2 is connected to the node V_C2. Although the transistor 143 isshown as an OS transistor, it may be a Si transistor. FIG. 8 illustratesan example where the potential of a ground line is supplied as apotential for initializing the node V_C2 connected to the transistor143.

The transistor 143 can initialize the potential of the node V_C2 bybeing turned on in response to a reset signal RESET supplied to itsgate. When the transistor 123 remains on, the node V_C2 is kept at apotential corresponding to charge distributed among the node V_C1 andthe node V_C2. Providing the transistor for initialization as in theconfiguration of FIG. 8 enables initialization at an opportune time.

The potential of the node V_C2 is initialized after data saved from thememory circuit 110 is restored to the memory circuit 110. Since dataheld in the memory circuit 120 is not necessary after the data isrestored to the memory circuit 110, initialization can be performed, forexample, by setting the reset signal RESET at H level after datarestoration.

VARIATION EXAMPLE 4

FIG. 9 is a circuit diagram illustrating a configuration example of asemiconductor device 60 in which the transistor 124 and the transistor125 in the semiconductor device 10 of FIG. 1 are a p-channel transistor124_p and an n-channel transistor, respectively.

Transistors of different conductivity types are used as the transistors124 and 125 that are controlled to be alternately turned on and off,whereby one of the control signal RE and the control signal RE_b can beomitted and only the other thereof can be supplied to gates of thetransistors 124 and 125. Thus, the number of kinds of signals input tothe semiconductor device can be reduced.

VARIATION EXAMPLE 5

FIG. 10 is a circuit diagram illustrating a configuration example of asemiconductor device 70 different from the semiconductor device 10 ofFIG. 1 in that a backgate signal OS_BG for controlling the thresholdvoltage is applied to backgates of the transistors 121 and 123.

Supply of the backgate signal OS_BG to the backgates of the transistors121 and 123 can control the threshold voltages. If the thresholdvoltages of the transistors 121 and 123 fluctuate and the off-stateleakage current increases as a result, charge might not be held at thenode Node_M. For this reason, controlling the threshold voltages bysupplying the backgate signal OS_BG in advance allows the node Node_M tohold charge reliably. Moreover, controlling the threshold voltage of thetransistor reduces the voltage amplitude of a signal supplied to itsgate, resulting in lower power consumption.

VARIATION EXAMPLE 6

FIG. 11 is a circuit diagram illustrating a configuration example of asemiconductor device 80 different from the semiconductor device 10 ofFIG. 1 in that a ground potential that is an L-level potential forshifting the threshold voltage in the positive direction is supplied tothe backgates of the transistors 121 and 123.

With the configuration in FIG. 11, the threshold voltages of thetransistors 121 and 123 can be shifted in the positive direction.Positive shift of the threshold voltage of the transistor reducesleakage current when an L-level potential of a signal supplied to itsgate is the ground potential. In the configuration in FIG. 11, it is notnecessary to supply the backgate signal OS_BG, so that the number ofkinds of signals input to the semiconductor device can be reduced.

VARIATION EXAMPLE 7

FIG. 12 is a circuit diagram illustrating a configuration example of asemiconductor device 90 different from the semiconductor device 10 ofFIG. 1 in that the transistors 124 and 125 are OS transistors instead ofSi transistors. Although not shown in FIG. 12, the transistor includedin the inverter circuit 128 can also be an OS transistor.

Using OS transistors as all the transistors included in the memorycircuit 120 eliminates steps and apparatuses for fabricating Sitransistors. As a result, costs for fabricating the semiconductor devicecan be reduced.

Variation examples of the semiconductor devices described in thisembodiment can be implemented in combination as appropriate, in whichcase it is possible to obtain the effects of the variation examples inaddition to the effect of the semiconductor device described inEmbodiment 1. Thus, a high-performance semiconductor device can beprovided.

The structure described in this embodiment can be used as appropriate incombination with any of the structures described in the otherembodiments.

Embodiment 3

This embodiment will explain an oxide semiconductor layer that can beused as a semiconductor layer including a channel formation region ofthe transistor with low off-state current described in the foregoingembodiments.

An oxide semiconductor used for the semiconductor layer including achannel formation region of the transistor preferably contains at leastindium (In) or zinc (Zn). In particular, the oxide semiconductorpreferably contains both In and Zn. The oxide semiconductor preferablycontains a stabilizer for strongly bonding oxygen, in addition to In andZn. The oxide semiconductor preferably contains at least one of gallium(Ga), tin (Sn), zirconium (Zr), hafnium (Hf), and aluminum (Al) as thestabilizer.

As another stabilizer, the oxide semiconductor may contain one or morekinds of lanthanoid such as lanthanum (La), cerium (Ce), praseodymium(Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd),terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm),ytterbium (Yb), and lutetium (Lu).

As the oxide semiconductor used for the semiconductor layer including achannel formation region of the transistor, any of the following can beused, for example: indium oxide, tin oxide, zinc oxide, In—Zn-basedoxide, Sn—Zn-based oxide, Al—Zn-based oxide, Zn—Mg-based oxide,Sn—Mg-based oxide, In—Mg-based oxide, In—Ga-based oxide, In—Ga—Zn-basedoxide (also referred to as IGZO), In—Al—Zn-based oxide, In—Sn—Zn-basedoxide, Sn—Ga—Zn-based oxide, Al—Ga—Zn-based oxide, Sn—Al—Zn-based oxide,In—Hf—Zn-based oxide, In—Zr—Zn-based oxide, In—Ti—Zn-based oxide,In—Sc—Zn-based oxide, In—Y—Zn-based oxide, In—La—Zn-based oxide,In—Ce—Zn-based oxide, In—Pr—Zn-based oxide, In—Nd—Zn-based oxide,In—Sm—Zn-based oxide, In—Eu—Zn-based oxide, In—Gd—Zn-based oxide,In—Tb—Zn-based oxide, In—Dy—Zn-based oxide, In—Ho—Zn-based oxide,In—Er—Zn-based oxide, In—Tm—Zn-based oxide, In—Yb—Zn-based oxide,In—Lu—Zn-based oxide, In—Sn—Ga—Zn-based oxide, In—Hf—Ga—Zn-based oxide,In—Al—Ga—Zn-based oxide, In—Sn—Al—Zn based oxide, In—Sn—Hf—Zn-basedoxide, and In—Hf—Al—Zn-based oxide.

For example, an In—Ga—Zn-based oxide with an atomic ratio ofIn:Ga:Zn=1:1:1, 3:1:2, or 2:1:3 or an oxide with an atomic ratio closeto the above atomic ratios can be used.

If an oxide semiconductor film forming the semiconductor layer includinga channel formation region contains a large amount of hydrogen, thehydrogen and the oxide semiconductor are bonded to each other, so thatpart of the hydrogen serves as a donor and causes generation of anelectron which is a carrier. As a result, the threshold voltage of thetransistor shifts in the negative direction. It is therefore preferablethat after formation of the oxide semiconductor film, dehydrationtreatment (dehydrogenation treatment) be performed to remove hydrogen ormoisture from the oxide semiconductor film so that the oxidesemiconductor film is highly purified to contain impurities as little aspossible.

Note that oxygen in the oxide semiconductor film is sometimes reduced bythe dehydration treatment (dehydrogenation treatment). For that reason,it is preferable that oxygen be added to the oxide semiconductor film tofill oxygen vacancies increased by the dehydration treatment(dehydrogenation treatment). In this specification and the like,supplying oxygen to an oxide semiconductor film may be expressed asoxygen adding treatment or treatment for making an oxygen-excess state.

In this manner, hydrogen or moisture is removed from the oxidesemiconductor film by the dehydration treatment (dehydrogenationtreatment) and oxygen vacancies therein are filled by the oxygen addingtreatment, whereby the oxide semiconductor film can be turned into ani-type (intrinsic) oxide semiconductor film or a substantially i-type(intrinsic) oxide semiconductor film that is extremely close to ani-type oxide semiconductor film. Note that “substantially intrinsic”means that the oxide semiconductor film contains extremely few (close tozero) carriers derived from a donor and has a carrier density of1×10¹⁷/cm³ or lower, 1×10¹⁶/cm³ or lower, 1×10¹⁵/cm³ or lower,1×10¹⁴/cm³ or lower, or 1×10¹³/cm³ or lower.

The transistor including an i-type or substantially i-type oxidesemiconductor film can have extremely favorable leakage currentcharacteristics. For example, the off-state drain current of thetransistor including the oxide semiconductor film can be 1×10⁻¹⁸ A orless, preferably 1×10⁻²¹ A or less, more preferably 1×10⁻²⁴ A or less atroom temperature (approximately 25° C.), or 1×10⁻¹⁵ A or less,preferably 1×10⁻¹⁸ A or less, more preferably 1×10⁻²¹ A or less at 85°C. Note that the off state of an n-channel transistor refers to a statewhere a gate voltage is sufficiently lower than the threshold voltage.Specifically, the transistor is off when the gate voltage is lower thanthe threshold voltage by 1 V or more, 2 V or more, or 3 V or more.

An oxide semiconductor film may include a non-single crystal, forexample. The non-single crystal state is structured, for example, by atleast one of c-axis aligned crystal (CAAC), polycrystal, microcrystal,and an amorphous part.

An oxide semiconductor may include CAAC, for example. Note that an oxidesemiconductor including CAAC is referred to as a c-axis alignedcrystalline oxide semiconductor (CAAC-OS).

In an image obtained with a transmission electron microscope (TEM), forexample, crystal parts can be found in the CAAC-OS in some cases. Inmost cases, in an image obtained with a TEM, crystal parts in theCAAC-OS each fit inside a cube whose one side is less than 100 nm, forexample. In an image of the CAAC-OS obtained with a TEM, a boundarybetween the crystal parts or a grain boundary is not clearly observed insome cases. Since a clear grain boundary does not exist in the CAAC-OS,segregation of an impurity, high density of defect states, or areduction in electron mobility is unlikely to occur, for example.

For example, the CAAC-OS sometimes includes a plurality of crystal partswhose c-axes are aligned in a direction parallel to a normal vector of asurface where the CAAC-OS is formed or a normal vector of a surface ofthe CAAC-OS. When the CAAC-OS is analyzed by an out-of-plane method withan X-ray diffraction (XRD) apparatus, a peak at 2θ of around 31° whichshows alignment appears in some cases. Furthermore, for example, spots(luminescent spots) are observed in an electron diffraction pattern ofthe CAAC-OS in some cases. Note that an electron diffraction patternobtained with an electron beam having a beam diameter of 10 nmφ orsmaller or 5 nmφ or smaller is called a nanobeam electron diffractionpattern. In the CAAC-OS, for example, among crystal parts, thedirections of the a-axis and the b-axis of one crystal part aresometimes different from those of another crystal part. In the CAAC-OS,for example, c-axes are aligned and a-axes and/or b-axes are notmacroscopically aligned in some cases.

In each of the crystal parts included in the CAAC-OS, for example, thec-axis is aligned in a direction parallel to a normal vector of asurface where the CAAC-OS is formed or a normal vector of a surface ofthe CAAC-OS, metal atoms are arranged in a triangular or hexagonalpattern when seen from the direction perpendicular to the a-b plane, andmetal atoms are arranged in a layered manner or metal atoms and oxygenatoms are arranged in a layered manner when seen from the directionperpendicular to the c-axis. Note that among crystal parts, thedirections of the a-axis and the b-axis of one crystal part may bedifferent from those of another crystal part. In this specification, theterm “perpendicular” includes a range from 80° to 100°, preferably from85° to 95°, and the term “parallel” includes a range from −10° to 10°,preferably from −5° to 5°.

The CAAC-OS can be formed by reduction in the density of defect states,for example. In an oxide semiconductor, for example, oxygen vacanciesare defect states. Oxygen vacancies serve as trap levels or serve ascarrier generation sources when hydrogen is trapped therein. In order toform the CAAC-OS, for example, it is important to prevent oxygenvacancies from being generated in the oxide semiconductor. Thus, theCAAC-OS is an oxide semiconductor having a low density of defect states.In other words, the CAAC-OS is an oxide semiconductor having few oxygenvacancies.

The state in which impurity concentration is low and density of defectstates is low (the number of oxygen vacancies is small) is referred toas a “highly purified intrinsic” or “substantially highly purifiedintrinsic” state. A highly purified intrinsic or substantially highlypurified intrinsic oxide semiconductor has few carrier generationsources, and thus has a low carrier density in some cases. Thus, in somecases, a transistor including the oxide semiconductor in a channelformation region rarely has a negative threshold voltage (is rarelynormally-on). A highly purified intrinsic or substantially highlypurified intrinsic oxide semiconductor has a low density of defectstates and accordingly has low density of trap states in some cases.Thus, the transistor including the oxide semiconductor in the channelformation region has a small change in electrical characteristics andhigh reliability in some cases. A charge trapped by the trap states inthe oxide semiconductor takes a long time to disappear. The trappedcharge may behave like a fixed charge. Consequently, the transistor thatcontains the oxide semiconductor having a high density of trap states inthe channel formation region has unstable electrical characteristics insome cases.

With the use of the highly purified intrinsic or substantially highlypurified intrinsic CAAC-OS in a transistor, a change in the electricalcharacteristics of the transistor due to irradiation with visible lightor ultraviolet light is small.

An oxide semiconductor may include polycrystal, for example. Note thatan oxide semiconductor including polycrystal is referred to as apolycrystalline oxide semiconductor. A polycrystalline oxidesemiconductor includes a plurality of crystal grains.

An oxide semiconductor may include microcrystal, for example. Note thatan oxide semiconductor including microcrystal is referred to as amicrocrystalline oxide semiconductor.

In an image obtained with a TEM, for example, crystal parts cannot befound clearly in the microcrystalline oxide semiconductor in some cases.In most cases, the size of a crystal part included in themicrocrystalline oxide semiconductor ranges from 1 nm to 100 nm, or from1 nm to 10 nm, for example. A microcrystal with a size ranging from 1 nmto 10 nm is specifically referred to as nanocrystal (nc). An oxidesemiconductor including nanocrystal is referred to as a nanocrystallineoxide semiconductor (nc-OS). In an image of the nc-OS obtained with aTEM, for example, a boundary between crystal parts is not clearlyobserved in some cases. Since a clear grain boundary does not exist inan image of the nc-OS obtained with a TEM, for example, segregation ofan impurity is unlikely to occur. In the nc-OS, since a clear grainboundary does not exist, high density of defect states or a reduction inelectron mobility is unlikely to occur, for example.

In the nc-OS, for example, a microscopic region (e.g., a region rangingfrom 1 nm to 10 nm) has a periodic atomic order occasionally.Furthermore, for example, in the nc-OS, crystal parts are not regularlyarranged. Thus, there is a case where periodic atomic order is notobserved macroscopically or a case where long-range order in atomicarrangement is not observed. Accordingly, in some cases, the nc-OScannot be distinguished from an amorphous oxide semiconductor, forexample, depending on an analysis method. When the nc-OS is analyzed byan out-of-plane method with an XRD apparatus using an X-ray having abeam diameter larger than the diameter of a crystal part, a peak thatshows alignment does not appear in some cases. Moreover, for example, ahalo pattern is shown in some cases in an electron diffraction patternof the nc-OS obtained by using an electron beam having a beam diameterlarger than the diameter of a crystal part (e.g., a beam diameter of 20nmφ or more, or 50 nmφ or more). For example, spots are shown in somecases in a nanobeam electron diffraction pattern of the nc-OS obtainedby using an electron beam having a beam diameter smaller than or equalto the diameter of a crystal part (e.g., a beam diameter of 10 nmφ orless, or 5 nmφ or less). In a nanobeam electron diffraction pattern ofthe nc-OS, for example, regions with high luminance in a circularpattern are shown in some cases. Moreover, in a nanobeam electrondiffraction pattern of the nc-OS, for example, a plurality of spots areshown in the region in some cases.

Since the microscopic region in the nc-OS has a periodic atomic orderoccasionally, the nc-OS has lower density of defect states than theamorphous oxide semiconductor. Note that since crystal parts in thenc-OS are not regularly arranged, the nc-OS has higher density of defectstates than the CAAC-OS.

Note that an oxide semiconductor film may be a mixed film including twoor more of a CAAC-OS, a polycrystalline oxide semiconductor, amicrocrystalline oxide semiconductor, and an amorphous oxidesemiconductor. The mixed film may include at least two of an amorphousoxide semiconductor region, a microcrystalline oxide semiconductorregion, a polycrystalline oxide semiconductor region, and a CAAC-OSregion, for example. Moreover, the mixed film may have a stackedstructure of at least two of an amorphous oxide semiconductor region, amicrocrystalline oxide semiconductor region, a polycrystalline oxidesemiconductor region, and a CAAC-OS region.

This embodiment can be implemented in appropriate combination with anyof the other embodiments.

Embodiment 4

Referring to a drawing, this embodiment will show a cross-sectionalstructure of transistors included in the semiconductor device of oneembodiment of the disclosed invention.

FIG. 13 illustrates an example of part of a cross-sectional structure ofthe semiconductor device. FIG. 13 illustrates the transistor 121, thecapacitor 122, the transistor 123, the transistor 125, and the capacitor127 shown in Embodiment 1.

In the cross-sectional view in FIG. 13, the transistor 121, thecapacitor 122, the transistor 123, the transistor 125 and the capacitor127 shown in FIG. 1 are denoted by the same reference numerals.

The cross-sectional view in FIG. 13 shows an example where thetransistor 125 is formed on a single crystal silicon substrate and thetransistors 121 and 123 using an oxide semiconductor for a semiconductorlayer including a channel formation region are formed over thetransistor 125. In the transistor 125, a thin semiconductor layer ofsilicon, germanium, or the like in an amorphous, microcrystalline,polycrystalline, or single crystal state may be used for thesemiconductor layer including a channel formation region.

In the cross-sectional view in FIG. 13, the transistors 121 and 123 aretransistors in which an oxide semiconductor provided in the same layeris used for a semiconductor layer including a channel formation region.Alternatively, the transistors 121 and 123 may be provided in differentlayers and stacked, in which case the density of semiconductor devicescan be further increased.

When the Si transistor and the OS transistors are stacked in thesemiconductor device as in FIG. 13, the chip area of the semiconductordevice can be reduced.

In FIG. 13, the n-channel transistor 125 is formed on a semiconductorsubstrate 810. Although not shown in FIG. 13, the transistor 124, thetransistors included in the inverter circuit 128, and the transistorsincluded in the memory circuit 110 can be provided in the same layer asthe transistor 125.

The semiconductor substrate 810 can be, for example, an n-type or p-typesilicon substrate, germanium substrate, silicon germanium substrate, orcompound semiconductor substrate (e.g., GaAs substrate, InP substrate,GaN substrate, SiC substrate, GaP substrate, GaInAsP substrate, or ZnSesubstrate). In FIG. 13, a single crystal silicon substrate having n-typeconductivity is used.

The transistor 125 is electrically isolated from other transistorsexisting in the same layer by element isolation insulating films 812.The element isolation insulating films 812 can be formed by a localoxidation of silicon (LOCOS) method, a trench isolation method, or thelike.

Specifically, the transistor 125 includes impurity regions 814 and 816that are formed in the semiconductor substrate 810 and function assource and drain regions, a conductive film 818, and a gate insulatingfilm 820 provided between the semiconductor substrate 810 and theconductive film 818. The conductive film 818 overlaps a channelformation region between the impurity regions 814 and 816 with the gateinsulating film 820 positioned between the conductive film 818 and thechannel formation region. Note that the conductive film 818 functions asa gate electrode.

An insulating film 822 is provided over the transistor 125. Openings areformed in the insulating film 822. A conductive film 824 in contact withthe impurity region 814, a conductive film 826 in contact with theimpurity region 816, and a conductive film 828 in contact with theconductive film 818 are formed in the openings. A conductive film 832 isformed in the same layer as the conductive films 824, 826, and 828.

An insulating film 834 is provided over the conductive films 824, 826,828, and 832. Openings are formed in the insulating film 834. Aconductive film 836 that is a wiring in contact with the conductive film826 and a conductive film 838 in contact with the conductive film 832are formed in the openings.

In FIG. 13, the transistor 121, the capacitor 122, the transistor 123,and the capacitor 127 are formed over the insulating film 834.

The transistor 121 includes, over the insulating film 834, asemiconductor layer 842 containing an oxide semiconductor, conductivefilms 848 and 850 that are positioned over the semiconductor layer 842and function as source and drain electrodes, a gate insulating film 852over the semiconductor layer 842 and the conductive films 848 and 850,and a conductive film 858 that is positioned over the gate insulatingfilm 852 and overlaps the semiconductor layer 842 between the conductivefilms 848 and 850. Note that the conductive film 858 functions as a gateelectrode.

The capacitor 122 includes, over the insulating film 834, the conductivefilm 848, the gate insulating film 852 over the conductive film 848, anda conductive film 856 which is over the gate insulating film 852 andpart of which overlaps the conductive film 848.

The transistor 123 includes, over the insulating film 834, asemiconductor layer 840 containing an oxide semiconductor, conductivefilms 844 and 846 that are positioned over the semiconductor layer 840and function as source and drain electrodes, the gate insulating film852 over the semiconductor layer 840 and the conductive films 844 and846, and a conductive film 854 that is positioned over the gateinsulating film 852 and has a portion functioning as a gate electrode ina region overlapping the semiconductor layer 840 without overlapping theconductive films 844 and 846. The conductive film 844 is connected tothe conductive film 836. The conductive film 846 is connected to theconductive film 838. An opening reaching the conductive film 848 isformed in the gate insulating film 852. A conductive film 854 isprovided in the opening.

The capacitor 127 includes, over the insulating film 834, the conductivefilm 844, the gate insulating film 852 over the conductive film 844, anda conductive film 830 which is over the gate insulating film 852 andpart of which overlaps the conductive film 844.

An opening reaching the conductive film 850 is formed in the gateinsulating film 852 and an insulating film 860. A conductive film 862 isprovided in the opening.

Note that the conductive film 858 serves as a wiring supplied with thewrite control signal described in Embodiment 1. The conductive film 832serves as a ground line supplied with the ground potential described inEmbodiment 1. The conductive films 848 and 854 serve as wiringscorresponding to the node Node_M described in Embodiment 1. Theconductive films 826, 836, and 844 serve as wirings corresponding to thenode V_C2 described in Embodiment 1. The conductive film 862 serves as awiring corresponding to the node Node_in described in Embodiment 1.

As the gate insulating films 820 and 852, an inorganic insulating filmmay be used, for example. The inorganic insulating film preferably has asingle-layer or multi-layer structure including any of a silicon nitridefilm, a silicon oxynitride film, a silicon nitride oxide film, and thelike. Providing the gate insulating films 820 and 852 in differentlayers enables them to have different thicknesses easily. In oneembodiment of the present invention, the thickness of the gateinsulating film 852 of the transistor 123 is larger than that of thegate insulating film 820 of the transistors 124 and 125 as described inEmbodiment 1. This structure can suppress degradation of chargeretention characteristics due to gate leakage current of the transistor123, thereby providing a novel-structured semiconductor device withexcellent charge retention characteristics of a node for retainingcharge.

Each of the insulating films 822, 834, and 860 is preferably a singlelayer or a multilayer including an inorganic insulating film or anorganic insulating film. The organic insulating film preferably has asingle-layer or a multi-layer structure containing polyimide, acrylic,or the like.

The semiconductor layers 840 and 842 are preferably formed using anoxide semiconductor. The oxide semiconductor can be any of the materialsdescribed in Embodiment 3.

Each of the conductive films 818, 824, 826, 828, 830, 832, 836, 838,844, 846, 848, 850, 854, 856, 858, and 862 can be, for example, a singlelayer or a stack containing a metal material such as aluminum, copper,titanium, tantalum, or tungsten.

In FIG. 13, the transistors 121 and 123 have the gate electrode on atleast one side of the semiconductor layer; alternatively, they may havea pair of gate electrodes with the semiconductor layer positionedtherebetween.

When the transistors 121 and 123 include a pair of gate electrodes withthe semiconductor layer positioned therebetween, one of the gateelectrodes may be supplied with a signal for controlling the on/offstate, and the other of the gate electrodes may be supplied with apotential from another element. In the latter case, potentials with thesame level may be supplied to the pair of gate electrodes, or a fixedpotential such as a ground potential may be supplied only to the otherof the gate electrodes. When the level of a potential supplied to theother of the gate electrodes is controlled, the threshold voltage of thetransistors 121 and 123 can be controlled.

The semiconductor layers 840 and 842 are not limited to a single film ofan oxide semiconductor and may be a stack including a plurality of oxidesemiconductor films.

The structure described in this embodiment provides a semiconductordevice with excellent charge retention characteristics of a node forretaining charge as described in Embodiment 1. Furthermore, with thestructure of this embodiment, the increase in the circuit area due tothe increase in the number of elements can be prevented, and asemiconductor device with high area efficiency can be provided.

This embodiment can be implemented in appropriate combination with anyof the other embodiments.

Embodiment 5

In this embodiment, application examples of the semiconductor devicedescribed in the foregoing embodiment to an electronic component and toan electronic device including the electronic component will bedescribed with reference to FIGS. 14A and 14B and FIGS. 15A to 15E.

FIG. 14A shows an example where the semiconductor device described inthe foregoing embodiment is used to make an electronic component. Notethat an electronic component is also referred to as semiconductorpackage or IC package. For the electronic component, there are variousstandards and names corresponding to the direction of terminals or theshape of terminals; hence, one example of the electronic component willbe described in this embodiment.

A semiconductor device including the transistors illustrated in FIG. 13of Embodiment 4 is completed by integrating detachable components on aprinted circuit board through the assembly process (post-process).

The post-process can be completed through steps shown in FIG. 14A.Specifically, after an element substrate obtained in the wafer processis completed (Step S1), a back surface of the substrate is ground (StepS2). The substrate is thinned in this step to reduce warpage or the likeof the substrate in the wafer process and to reduce the size of thecomponent itself.

A dicing step of grinding the back surface of the substrate to separatethe substrate into a plurality of chips is performed. Then, a diebonding step of individually picking up separate chips to be mounted onand bonded to a lead frame is performed (Step S3). To bond a chip and alead frame in the die bonding step, resin bonding, tape-automatedbonding, or the like is selected as appropriate depending on products.Note that in the die bonding step, a chip may be mounted on and bondedto an interposer.

Next, wire bonding for electrically connecting a lead of the lead frameand an electrode on a chip through a metal wire is performed (Step S4).As a metal wire, a silver wire or a gold wire can be used. For wirebonding, ball bonding or wedge bonding can be employed.

A wire-bonded chip is subjected to a molding step of sealing the chipwith an epoxy resin or the like (Step S5). With the molding step, theinside of the electronic component is filled with a resin, so that thecircuit portion and the wire embedded in the component can be protectedfrom external mechanical force and deterioration of characteristics dueto moisture or dust can be reduced.

Subsequently, the lead of the lead frame is plated. Then, the lead iscut and processed into a predetermined shape (Step S6). With the platingprocess, corrosion of the lead can be prevented, and soldering formounting the electronic component on a printed circuit board in a laterstep can be performed with higher reliability.

Next, printing process (marking) is performed on a surface of thepackage (Step S7). Then, through a final test step (Step S8), theelectronic component is completed (Step S9).

Since the electronic component described above includes thesemiconductor device of the foregoing embodiment, it is possible toobtain an electronic component including the semiconductor device inwhich the node for retaining charge has excellent charge retentioncharacteristics. The electronic component has excellent data retentioncharacteristics because it includes the semiconductor device of theforegoing embodiment.

FIG. 14B is a perspective schematic diagram of a completed electroniccomponent. FIG. 14B shows a perspective schematic diagram of a quad flatpackage (QFP) as an example of the electronic component. An electroniccomponent 700 illustrated in FIG. 14B includes a lead 701 and asemiconductor device 703. The electronic component 700 in FIG. 14B is,for example, mounted on a printed circuit board 702. A plurality ofelectronic components 700 are used in combination and electricallyconnected to each other over the printed wiring board 702; thus, asubstrate on which the electronic components are mounted (a circuitboard 704) is completed. The completed circuit board 704 is provided inan electronic device or the like.

Next, the description is made on applications of the above electroniccomponent to electronic devices such as a computer, a portableinformation appliance (including a mobile phone, a portable gamemachine, and an audio reproducing device), electronic paper, atelevision device (also referred to as television or televisionreceiver), and a digital video camera.

FIG. 15A illustrates a portable information appliance that includes ahousing 901, a housing 902, a first display portion 903a, a seconddisplay portion 903b, and the like. At least one of the housings 901 and902 includes the circuit board including the semiconductor device of theforegoing embodiment. Thus, it is possible to obtain a portableinformation appliance with excellent charge retention characteristics.

Note that the first display portion 903a is a panel having a touch inputfunction, and for example, as illustrated in the left of FIG. 15A, whichof “touch input” and “keyboard input” is performed can be selected by aselection button 904 displayed on the first display portion 903 a. Sinceselection buttons with a variety of sizes can be displayed, theinformation appliance can be easily used by people of any generation.For example, when “keyboard input” is selected, a keyboard 905 isdisplayed on the first display portion 903 a as illustrated in the rightof FIG. 15A. Thus, letters can be input quickly by key input as in thecase of using a conventional information appliance, for example.

One of the first display portion 903a and the second display portion 903b can be detached from the portable information appliance as shown inthe right of FIG. 15A. Providing the second display portion 903 b with atouch input function makes the information appliance convenient to carrybecause the weight can be further reduced and the information appliancecan operate with one hand while the other hand supports the housing 902.

The portable information appliance in FIG. 15A can be equipped with afunction of displaying a variety of information (e.g., a still image, amoving image, and a text image); a function of displaying a calendar, adate, the time, or the like on the display portion; a function ofoperating or editing information displayed on the display portion; afunction of controlling processing by various kinds of software(programs); and the like. Furthermore, an external connection terminal(e.g., an earphone terminal or a USB terminal), a recording mediuminsertion portion, and the like may be provided on the back surface orthe side surface of the housing.

The portable information appliance illustrated in FIG. 15A may transmitand receive data wirelessly. Through wireless communication, desiredbook data or the like can be purchased and downloaded from an e-bookserver.

In addition, the housing 902 illustrated in FIG. 15A may be equippedwith an antenna, a microphone function, or a wireless communicationfunction to be used as a mobile phone.

FIG. 15B illustrates an e-book reader in which electronic paper isincorporated. The e-book reader has two housings of a housing 911 and ahousing 912. The housing 911 and the housing 912 are provided with adisplay portion 913 and a display portion 914, respectively. Thehousings 911 and 912 are connected by a hinge 915 and can be opened orclosed with the hinge 915 as an axis. The housing 911 is provided with apower switch 916, an operation key 917, a speaker 918, and the like. Thecircuit board including the semiconductor device of the foregoingembodiment is provided in at least one of the housings 911 and 912.Consequently, it is possible to obtain an e-book reader with excellentcharge retention characteristics.

FIG. 15C illustrates a television device including a housing 921, adisplay portion 922, a stand 923, and the like. The television devicecan operate with a switch of the housing 921 and a separate remotecontroller 924. The circuit board including the semiconductor device ofthe foregoing embodiment is mounted on the housings 921 and the remotecontroller 924. Thus, it is possible to obtain a television withexcellent charge retention characteristics.

FIG. 15D illustrates a smartphone in which a main body 930 is providedwith a display portion 931, a speaker 932, a microphone 933, anoperation key 934, and the like. The circuit board including thesemiconductor device of the foregoing embodiment is provided in the mainbody 930. Thus, it is possible to obtain a smartphone with excellentcharge retention characteristics.

FIG. 15E illustrates a digital camera including a main body 941, adisplay portion 942, an operation switch 943, and the like. The circuitboard including the semiconductor device of the foregoing embodiment isprovided in the main body 941. Thus, it is possible to obtain a digitalcamera with excellent charge retention characteristics.

As described above, the electronic devices shown in this embodimentincorporate the circuit board including the semiconductor device of theforegoing embodiment, thereby having excellent charge retentioncharacteristics.

This application is based on Japanese Patent Application serial No.2013-169830 filed with Japan Patent Office on Aug. 19, 2013, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a first circuit; anda second circuit, the second circuit comprising: a first transistorcomprising a first gate, a first source, and a first drain; a secondtransistor comprising a second gate, a second source, and a seconddrain; a third transistor comprising a third gate, a third source, and athird drain; a fourth transistor comprising a fourth gate, a fourthsource, and a fourth drain; and an inverter, wherein one of the firstsource and the first drain of the first transistor is electricallyconnected to a first node in the first circuit, wherein the other of thefirst source and the first drain of the first transistor is electricallyconnected to a third node and the second gate of the second transistor,wherein one of the third source and the third drain of the thirdtransistor is electrically connected to one of the fourth source and thefourth drain of the fourth transistor, wherein the other of the fourthsource and the fourth drain of the fourth transistor is electricallyconnected to one of the second source and the second drain of the secondtransistor, and an input terminal of the inverter, and wherein an outputterminal of the inverter is electrically connected to a second node inthe first circuit.
 3. The semiconductor device according to claim 2,wherein each of the first transistor and the second transistor comprisesa channel formation region provided in an oxide semiconductor layer. 4.The semiconductor device according to claim 2, wherein a channelformation region of each of the third transistor and the fourthtransistor comprises silicon.
 5. The semiconductor device according toclaim 2, further comprising a first capacitor and a second capacitor,wherein the one of the third source and the third drain of the thirdtransistor is electrically connected to one of a pair of firstelectrodes of the first capacitor, and wherein the one of the secondsource and the second drain of the second transistor is electricallyconnected to one of a pair of second electrodes of the second capacitor.6. The semiconductor device according to claim 5, further comprising athird capacitor, wherein the other of the first source and the firstdrain of the first transistor is electrically connected to one of a pairof third electrodes of the third capacitor.
 7. The semiconductor deviceaccording to claim 2, wherein the first transistor and the secondtransistor are stacked over the third transistor and the fourthtransistor.
 8. The semiconductor device according to claim 6, whereinthe first circuit stores data at the first node and the second node in aperiod during which a power supply voltage is supplied, wherein thesecond circuit stores the data at the third node when a first controlsignal is supplied to the first gate of the first transistor, whereinwhen the data is not read, a second control signal is supplied to thethird gate of the third transistor, and the third transistor storescharge in the first capacitor, wherein when the data is read, the fourthtransistor distributes the charge stored in the first capacitor to thesecond capacitor, and wherein when the data is read, the secondtransistor makes a first potential held in the second capacitor a secondpotential by inverting logic of the data, in accordance with a potentialof the data at the third node.
 9. The semiconductor device according toclaim 2, further comprising a fifth transistor comprising a fifth gate,a fifth source, and a fifth drain, wherein a channel formation region ofthe fifth transistor comprises silicon, wherein the one of the secondsource and the second drain of the second transistor is connected to oneof the fifth source and the fifth drain of the fifth transistor, andwherein the other of the second source and the second drain of thesecond transistor is connected to the fifth gate of the fifthtransistor.
 10. The semiconductor device according to claim 2, whereineach of the first transistor and the second transistor further comprisesa backgate electrode.
 11. The semiconductor device according to claim 8,further comprising a sixth transistor comprising a sixth gate, a sixthsource, and a sixth drain, wherein one of the sixth source and the sixthdrain of the sixth transistor is electrically connected to the one ofthe pair of second electrodes of the second capacitor, and wherein thesixth transistor supplies a potential for initializing the secondpotential held in the second capacitor.
 12. The semiconductor deviceaccording to claim 5, wherein capacitance of the first capacitor islarger than capacitance of the second capacitor.
 13. The semiconductordevice according to claim 2, wherein a thickness of a gate insulatingfilm of the second transistor is larger than a thickness of a gateinsulating film of the third transistor and the fourth transistor. 14.The semiconductor device according to claim 8, wherein the inverterinverts the second potential held in the second capacitor and suppliesan inverted potential to the second node.